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Features of the transition process of establishing the duration of output pulses in a braked relaxation oscillator with a shaping RS flip-flopEROFEEV, YU. N.Journal of communications technology & electronics. 1997, Vol 42, Num 5, pp 574-580, issn 1064-2269Article

Design of high performance double edge-triggered flip-flopsMISHRA, S. M; ROFAIL, S. S; YEO, K. S et al.IEE proceedings. Circuits, devices and systems. 2000, Vol 147, Num 5, pp 283-290, issn 1350-2409Article

Analysis of power dissipation in double edge-triggered flip-flopsSTROLLO, Antonio G. M; NAPOLI, Ettore; CIMINO, Carlo et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 624-629, issn 1063-8210Conference Paper

Low voltage, double-edge-triggered flip flopVARMA, Pradeep; CHAKRABORTY, Ashutosh.Lecture notes in computer science. 2003, pp 11-20, issn 0302-9743, isbn 3-540-20074-6, 10 p.Conference Paper

A novel 2.4 GHz CMOS dual-modulus prescaler using new implementation of phase-switching techniqueBAOYONG CHI; BINGXUE SHI.International journal of electronics. 2002, Vol 89, Num 6, pp 505-515, issn 0020-7217, 11 p.Article

Improving path delay testability of sequential circuitsCHAKRABORTY, Tapan J; AGRAWAL, Vishwani D; BUSHNELL, Michael L et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 6, pp 736-741, issn 1063-8210Article

Self-blocking flip-flop designLI, X; JIA, S; LIANG, X et al.Electronics letters. 2012, Vol 48, Num 2, pp 82-83, issn 0013-5194, 2 p.Article

Microthyristor-based sequential circuits and systemsHAFEZ, I. M; ZEKRY, A.International journal of electronics. 2004, Vol 91, Num 2, pp 119-135, issn 0020-7217, 17 p.Article

All-optical switching based on a three-order scattering of light by coherent acoustic phonons in single crystalsSHCHERBAKOV, Alexandre S; TEPICHIN RODRIGUEZ, Eduardo; AGUIRRE LOPEZ, Arturo et al.SPIE proceedings series. 2002, pp 239-247, isbn 0-8194-4555-X, 9 p.Conference Paper

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)TOKUMASU, Motoki; FUJII, Hiroshige; OHTA, Masako et al.Custom integrated circuits conference. 2002, pp 129-132, isbn 0-7803-7250-6, 4 p.Conference Paper

Deterministic built-in test pattern generation for high-performance circuits using twisted-ring countersCHAKRABARTY, Krishnendu; MURRAY, Brian T; IYENGAR, Vikram et al.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 633-636, issn 1063-8210Conference Paper

Noise metrics in flip-flop designsELGAMEL, Mohammed A; FAISAL, Md Ibrahim; BAYOUMI, Magdy A et al.IEICE transactions on information and systems. 2005, Vol 88, Num 7, pp 1501-1505, issn 0916-8532, 5 p.Article

High performance double edge-triggered flip-flop using a merged feedback techniqueMISHRA, S. M; ROFAIL, S. S; YEO, K.-S et al.IEE proceedings. Circuits, devices and systems. 2000, Vol 147, Num 6, pp 363-368, issn 1350-2409Article

Novel high-speed flip-flop circuit with low power consumption using GaAs junction FETsTAKANO, C; WADA, M; KASAHARA, J et al.Electronics Letters. 1991, Vol 27, Num 9, pp 764-765, issn 0013-5194, 2 p.Article

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect : Special Section on Solid-State Circuit Design-Architecture, Circuit, Device and Design MethodologyZHANG, Kuiyuan; FURUTA, Jun; YAMAMOTO, Ryosuke et al.IEICE transactions on electronics. 2013, Vol 96, Num 4, pp 511-517, issn 0916-8524, 7 p.Article

Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't caresNIKNAFS, Aliakbar; MOHAMMADI, Majid.Integration (Amsterdam). 2013, Vol 46, Num 2, pp 189-196, issn 0167-9260, 8 p.Article

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-FlopsCONSOLI, Elio; PALUMBO, Gaetano; PENNISI, Melita et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 2, pp 284-295, issn 1063-8210, 12 p.Article

Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data VolumeSONGWEI PEI; HUAWEI LI; XIAOWEI LI et al.IEEE transactions on very large scale integration (VLSI) systems. 2012, Vol 20, Num 12, pp 2157-2169, issn 1063-8210, 13 p.Article

Register isolation for synthesizable register filesMÜLLER, Matthias; WORTMANN, Andreas; MADER, Dominik et al.Lecture notes in computer science. 2004, pp 228-237, issn 0302-9743, isbn 3-540-23095-5, 10 p.Conference Paper

Optimization of scannable latches for low energyZYUBAR, Victor.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 5, pp 778-788, issn 1063-8210, 11 p.Article

Fabrication and voltage divider operation of a T flip-flop using high-Tc interface-engineered Josephson junctionsKIM, Junho; SANG HYEOB KIM; GUN YONG SUNG et al.Superconductor science & technology (Print). 2002, Vol 15, Num 9, pp 1320-1324, issn 0953-2048Article

Crosstalk-aware multi-bit flip-flop generation for power optimizationHSU, Chih-Cheng; LIN, Mark Po-Hung; CHANG, Yao-Tsung et al.Integration (Amsterdam). 2015, Vol 48, pp 146-157, issn 0167-9260, 12 p.Article

Pulse swallow frequency divider with idle DFFs automatically powered offHAIJUN GAO; LINGLING SUN; JUN LIU et al.Electronics letters. 2012, Vol 48, Num 11, pp 636-638, issn 0013-5194, 3 p.Article

Ultra High Density Standard Cell Library Using Multi-Height Cell StructureBAEK, Sang-Hoon; KIM, Ha-Young; LEE, Young-Keun et al.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 7268, issn 0277-786X, isbn 9780819475206, 72680C.1-72680C.8Conference Paper

A comparison of some circuit schemes for semi-reversible adiabatic logicBLOTTI, A; DI PASCOLI, S; SALETTI, R et al.International journal of electronics. 2002, Vol 89, Num 2, pp 147-158, issn 0020-7217Article

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